Method for producing a transistor with self-aligned contacts and field insulation

ABSTRACT

A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. Source and drain contacts are formed on the portion of the silicon film between the field insulation layer and the grid structure. The source and drain contacts are self-aligned on the grid structure and the field insulation layer is placed directly adjacent to the grid structure.

DESCRIPTION

1. Background of the Invention

This invention relates to a field effect transistor in which the fieldinsulation and contact areas are self-aligned with its active region,and a process for making this transistor.

More precisely, the invention relates to the manufacture of thistransistor on a Silicon On Insulator type substrate, subsequentlyreferred to as SOI in the rest of the text.

Applications of the invention include microelectronics for themanufacture of Metal Oxide Semiconductor (MOS) type devices, andparticularly for integrated circuits useable in an environment subjectto radiation.

2. Discussion of the Background

The state of the art closest to the invention is shown in FIG. 1 in theappendix. This figure diagramatically shows a cross-section through thestructure of a MOS type transistor 10 made on an SOI substrate. Theactive region 12 of the transistor 10 is formed in a silicon thin film14 covering a buried layer of silicon oxide SiO₂ 16.

The active region 12 is delimited by thick silicon oxide pads 17 of theLOCOS (LOCalized Oxidation of Silicon) type formed in the silicon thinfilm 14. The pads 17 mutually isolate the different transistors made onthe same SOI substrate. A grid structure 18 comprises a stack, with agrid insulator layer 20, a grid 22, and a shunt layer 24 forming acontact area on grid 20 and lateral spacers 26 formed on the stackflanks, in order.

The grid structure 18 is placed above the transistor channel 28 and thesource region 30 and drain region 32 are formed by doping the thin film14 on each side of the grid structure.

A thick layer 34 of BPSG (borophosphosilicate glass) type glass coversthe active region 12 and surrounds the grid structure 18.

Contact holes 36, 38 formed in the glass layer 34, vertically in linewith the source 30 and drain 32, and metal 40 formed in holes 36, 38form conductive tracks connecting the source and drain to metallicinterconnection lines 42, 44 respectively formed on layer 34.

A large number of photolithography steps are necessary to define itscomponents and to make a transistor according to FIG. 1.

A first step is necessary to form the field oxide pads 17. A secondphotolithography step is used to make the grid structure 18. Finally, aphotolithography step is necessary to make the contact holes in theglass layer 34.

Formation of the grid structure 18 comprises deposition of the gridinsulator layer 20, the grid layer 22 and the shunt layer 24, thenetching these layers using a mask defining the shape and dimensions ofthe grid structure. The position of the mask defining the grid withrespect to the mask used to define the oxide pads is difficult fordevices with high integration. Thus, the process is incapable of makinga very precise alignment of the grid on the active area, and carriertype inversion problems are observed on the flanks of the active area.These problems are due particularly to coupling between the grid and theflanks of the active area when the field insulation is partially removedin the field area.

Another difficulty in making the transistor in FIG. 1 is due to thealignment of contact holes on the source and drain regions. Thisdifficulty also forms a limitation to miniaturization of devices.

SUMMARY OF THE INVENTION

Thus, one purpose of the invention is to propose a transistor and itsmanufacturing process on an SOI substrate which does not have any of thedifficulties mentioned above.

Another purpose is particularly to propose a process in which firstlythe grid is automatically aligned with the active region comprising thechannel, and secondly the contact areas are automatically aligned withthe grid. Another purpose of the invention is to propose a process witha minimum number of photolithography steps.

Another purpose of the invention is to propose a transistor enablingtotal control with low inversion. The low inversion condition is thecondition in which the transistor is conducting under the conductinglimit at high inversion conditions. It is considered that total controlin low inversion is obtained when there is no current leak in theseoperating conditions.

Finally, another purpose of the invention is to propose a transistorcapable of operating in a "hostile" environment subject to ionizingradiation.

In order to achieve the purposes mentioned above, the subject of theinvention is more precisely a process for making a transistor on an SOItype support comprising a layer of insulating silicon oxide, called theburied oxide layer and a thin silicon film covering the buried oxidelayer, the process comprising the following steps in sequence:

a) formation of a stack on the thin silicon film, comprising a gridinsulator layer and a grid material layer, in order,

b) formation of a first etching mask according to a patterncorresponding to an active area of the transistor, on the stack,

c) etch the grid material layer, the grid insulator layer and the thinfilm, to form a column with first flanks defined according to thepattern of the first etching mask,

d) formation of a layer of electrical insulating material around thecolumn, and removing the surface of this layer stopping on the column,

e) etch the grid material layer in the column according to a second maskto form a grid structure with the second flanks,

f) electrical insulation of the flanks of the grid structure,

g) formation of the source and drain regions in the thin film byimplantation of impurities,

h) self-aligned formation of contact areas on the grid structure in thesource and drain regions.

The process according to the invention is particularly suitable for SOItype substrates for which the thin film is thinner than 20 nm. However,it can be implemented with other thicknesses.

Furthermore, the electrical insulation on the grid flanks and theformation of contact areas self-aligned on the grid avoids theconstraint of carrying out a precise check of the position of thecontact holes in the layer of electrical insulating material.

Note also that the process according to the invention only requires twophotolithography steps to form the transistor.

According to one aspect of the invention, in step a) the process mayalso include the formation of a protection layer above the layer of gridmaterial, the protection layer also being etched in step c), and forminga stop layer when removing the surface of the layer of insulatingmaterial in step d). The protection layer is eliminated after step d).

One function of the protection layer is to protect the upper part of thegrid from any oxidation. Thus, after the protection layer has beeneliminated, it is easier to form the contact area on the grid with aconnection line or a layer of conducting material called the "shunt".

According to another aspect of the invention, after step d) and afterexposing the grid material, the process may also include the formationof a "shunt" layer covering the layer of electrical insulating materialand coming into contact with the grid material, the shunt layer alsobeing etched during step e) according to the second etching mask, andthe second flanks of the shunt layer formed during step e), also beingelectrically insulated during step f).

The shunt layer, preferably made of a metal polysilicide, forms aconnection line for grid addressing.

According to one particular embodiment of the process, it may alsoinclude oxidation of the flanks of the column formed in step c), beforestep d), to cover them with a "flanks" oxide layer. This oxidationrounds the edges of the active region of the future transistor andfacilitates checking its characteristic in low inversion.

The flanks oxide layer will also act as an etching stop layer in step e.

The formation of contact areas on the source and drain regions does notrequire an additional photolithography step. For example, contact areasare formed by conform deposition of a metal layer, self-aligned with thegrid structure and by polishing this metal layer. The fact that there isno photolithography step for making the contact areas avoids difficultalignment problems and enables miniaturization of devices.

According to another aspect of the invention, the process may alsoinclude elimination of the grid oxide layer exposed on each side of thegrid during step e) and self-aligned silicidation of the metal layerwith the thin film exposed by elimination of the grid oxide layer. Dueto this measure, good contact is guaranteed between the source and drainregions and the metal layer.

Another purpose of the invention is a field effect transistor comprisinga source, a channel and a drain formed in a portion of silicon film in asilicon on insulator (SOI) type structure, a field insulation layeraround the sides of the portion of silicon film, a grid structure withinsulated flanks formed above the channel, and source and drain contactsformed on the portion of silicon film between the field insulation layerand the grid structure. According to the invention, the source and draincontacts are self-aligned on the grid structure and on the fieldinsulation layer and are directly placed adjacent to the flanks of thegrid structure. Furthermore, the contacts are delimited by a layer,called the flanks oxide layer, approximately perpendicular to theportion of the silicon film and self-aligned on the field insulationlayer.

Other characteristics and advantages of the invention will become clearfrom reading the following description, given for illustrative purposesonly and in no way restrictive, with reference to the figures in theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, already described, is a longitudinal diagrammatic sectionthrough a known type of MOS field effect transistor.

FIG. 2 is a diagrammatic section through a stack of layers on an SOItype substrate, from which a transistor can be made conform with theprocess according to the invention,

FIG. 3 is a diagrammatic section showing the formation of a column byetching the stack in FIG. 2,

FIGS. 4 and 5 are diagrammatic sections of the stack illustrating thecolumn being coated with a layer of insulating material and removing thesurface of the layer of insulating material,

FIG. 6 is a diagrammatic section through the stack illustrating theformation of a shunt layer on the structure in FIG. 5,

FIGS. 7 and 8 are sections along plane VI--VI shown in FIG. 6, making anangle of 90° with the plane of the section in FIGS. 1 to 6, andillustrating the manufacture of a grid structure,

FIGS. 9, 10 and 11 are sections through the stack along the cut plane inFIGS. 7 and 8 and illustrate the formation of contact areas on thetransistor source and drain regions,

FIG. 12 is a sectional view of a particular embodiment of a transistoraccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows the initial structure for manufacture of a transistor.

The transistor is made on an SOI substrate 100 comprising a thin siliconsurface film 102 fixed to a layer of insulating silicon oxide, calledthe buried layer 104.

The thin film 102 is preferably 50 nm thick or less.

A first oxide layer 106 is formed by oxidation of the silicon on thefree surface of the thin layer 102.

The layer 106 forms the insulating layer of the transistor grid that ismade.

A layer 108 called the grid material layer made for example ofpolycrystalline or amorphous silicon, is deposited on the grid insulatorlayer 106.

Finally a protection layer 110, for example made of silicon nitride oran oxide is deposited on layer 108 of grid material in order to recoverits free surface. This protection layer will subsequently be used as apolishing stop layer. The stack formed by layers 106, 108 and 110 isdenoted by the general reference 112.

A first etching mask 114, shown as a discontinuous line in FIG. 2, isformed on the stack 112, according to photolithography processes knownin themselves.

Mask 114 defines the dimensions of the active area of the transistorthat is made.

The remaining of the description is specifically related to theproduction of a single field effect transistor. However, several suchtransistors can be made simultaneously on the same substrate, forexample forming an integrated circuit. In this case, a mask is formed onstack 112 with several patterns similar to pattern 114 and definingactive regions for all the transistors.

After formation of the mask, layers 110, 108, 106 of the stack, and film102 of substrate 100, are etched. The buried oxide layer 104 is used asa stop layer during this etching.

After etching and eliminating the mask 114, a column 116 that can beseen in FIG. 3 is obtained. The column comprises portions of thin film102, the grid oxide layer 106, the grid layer 108 and the protectionlayer 110, in sequence. The portion of thin film 102 on column 116corresponds approximately to the active part of the transistor.

The flanks of column 116 are marked with reference 118.

After elimination of mask 114, the flanks 118 are oxidized. Thisoxidation particularly relates to the thin silicon film 102 and the gridmaterial 108 of the column 116. During this step, the protection layer110 limits (when an oxide is used) or prevents (when silicon nitride isused) oxidation of the upper surface of the grid material that itcovers.

FIG. 4 shows a section through the structure obtained. This figure showscharacteristic shapes of column 116 with the oxidized flanks.

A first characteristic shape is a bird's beak shape at the height of thegrid oxide layer 106. Another characteristic shape is rounding of thelower edges of the portion of thin silicon film remaining from column116.

These characteristic shapes are preferably obtained with hightemperature and/or high pressure oxidation. High temperature and/or highpressure oxidation refers to oxidation that takes place at a temperatureexceeding 1000° C. and a pressure exceeding 10⁵ Pa. High pressureoxidation is described in the document "High Pressure Oxidation ofSilicon in Dry Oxygen" by Liang N. Lie et al. in Solid-State Science andTechnology, December 1982, pages 2828-2833.

Due the rounded shape of the portion of the thin film, in other wordsthe future active region of the transistor, transistor leakage currentsunder low inversion conditions can be limited. Control of leakagecurrents under low inversion conditions, in other words below theconduction threshold, can reduce the consumption of the transistor whennot conducting.

The flanks oxide layer that covers the flanks 118 of column 116 isdenoted by reference 120. Its thickness may for example be between 5 and20 nm. A subsequent step in the process consists of forming a layer 122of electrical insulating material around column 116 to coat it. Thelayer 120 is shown in FIG. 4. For example the electrical insulatingmaterial may be a layer of oxide (glass) doped with PSG or BPSG typephosphorus.

After depositing layer 122 of insulating material, a heat treatment isapplied for its stabilization and plastic flow.

The function of the layer of insulating material (PSG or BPSG glass) isto mutually isolate the various transistors or components made on thesame substrate. Another function is to harden the transistors to resistionizing radiation.

Selective mechanochemical polishing ineffective on silicon nitrideremoves the surface of layer 122 of insulating material down to thesilicon nitride protection layer 110, that covers the grid materiallayer 108.

Then, after the protection layer has been eliminated, the structureshown in section in FIG. 5 is obtained. The layer of grid material 108is exposed and is approximately flush with the plane of the polishedsurface 124 of layer 122.

At this stage of the process, doping can be done by implantation ofsilicon in the grid layer. Impurities leading to a n or p typeconductivity are implanted.

The process continues, as shown in FIG. 6, by formation of a "shunt"layer 126 above the grid material layer. The shunt layer deposited as anuninterrupted plate also covers the polished surface of the insulatinglayer 122. The shunt layer 126 is preferably made of a refractory metalpolysilicide. It is covered by an undoped deposited oxide layer 128. Theshunt layer can improve the contact area on the grid and thus increasethe transistor operating rate. This layer, when it has been shaped, canalso form an access line for polarization of the grid, for example suchas a line of words.

A second etching mask 130 formed on the deposited oxide layer 128defines the location and dimensions of a grid structure 132 above theactive region of the transistor. Successive etching of the oxide layer128, the shunt layer 126 and the material layer 108, stopping on thegrid oxide layer 102 and on the flanks oxide layer 120, results in thestructure shown in FIG. 7.

Note that the FIG. 7 and subsequent figures show a section along planeVI--VI shown in FIG. 6, which is at an angle of 90° with the sectionplanes shown in the previous figures.

The lateral extension of the etchings according to the second mask 130is limited in the area above the portion of the thin film 102 by theflanks oxide 120. Etchings according to mask 130 thus clear the gridstructure 132 which is therefore necessarily in line with the remainingportion of thin film 102, in other words in line with the future activeregion of the transistor. The grid structure comprises the layer of gridmaterial 108, the shunt layer 126 and the deposited oxide layer 128,after shaping.

Advantageously, after elimination of mask 130, the process is continuedby oxidation of flanks 134 of the grid structure, in other words inparticular the layers of grid material 108 and the shunt layer 126. Itis also possible to make a thin oxide deposit directly on the flanks.

To form source and drain regions of the transistor, a first ionimplantation is done in the thin film 102 using the grid structure 132as an implantation mask. Doped regions formed during the firstimplantation are shown in FIG. 7 and identified by reference 135.

After the formation of lateral spacers 136 on the flanks of the gridstructure and on the flanks oxide layer 120 covering the insulatinglayer 122, a second implantation is made at a higher dose. Theimplantation is made with impurities that result in an n+ or p+conductivity depending on the type of transistor channel made.

After implantation, annealing is done and the structure in FIG. 8 isachieved. In this figure source and drain regions are marked withreferences 140 and 142 respectively.

Lateral spacers 136 are obtained by depositing a layer that isolates thegrid from contact areas 150 and 152, then by etching this layer byanisotropic etching, selectively with respect to the oxide on theflanks. Advantageously, this layer is made of silicon nitride. It may bemade of an oxide but its selectivity while etching spacers will not beas good. Lateral spacers 136 have the function of forming gradual sourceand drain regions and also of protecting, these regions close to thegrid and on the edge of the contact areas made later.

In particular, spacers 136 avoid or limit lateral etching of layer 122of insulating material (PSG) during the cleaning operations that precedethe formation of contact areas on drain and source regions.

The formation of contact areas on the source and drain regions ispreceded by eliminating the residual grid oxide layer around the gridstructure, so that part of the thin film 102 corresponding to the sourceand drain can be exposed.

During this operation, the oxidized flanks of the grid structure and theflanks oxide 120 covering the sides of the insulating material layer122, are protected by lateral spacers 136.

A metal layer 148, for example tungsten, is then formed by chemicalvapor phase deposition on the entire structure. As shown in FIG. 9, themetal layer 148 comes into contact with the exposed source and drainregions 140, 142 and surrounds the grid structure 132. The chemicalvapor deposition technique (CVD) can produce a conform deposit.

Furthermore, before depositing the metal layer 148, the free surface 124of the insulating material layer 122 may be covered with atitanium/tungsten layer 125, and advantageously a two layer system witha composition capable of performing diffusion barrier and contactbarrier functions. For example, it could be a Ti-W layer in acomposition close to stoechiometry. This layer, shown in FIG. 9, forms ametal bond layer and also acts as a metal diffusion barrier in theinsulation.

Advantageously, the source 140 and drain 142 are silicided before layer125 is deposited by selective silicidation on the exposed silicon.Silicidation can reduce the resistance at the metal-semiconductorinterface and thus improve contact areas on the source and drain. InFIG. 9, silicided parts are shown as reference 149.

As shown in FIG. 10, the next step is to polish the metal layer toremove its surface down to the silicon oxide layer 128 of the gridstructure 132. Layer 125 is subsequently polished.

Finally, as shown in FIG. 11, the metal layer and the bond layer may beetched to shape the contacts 150, 152. Other conventional metal orinsulation deposition operations can be carried out to form connectionsbetween the transistor and an integrated circuit. These operations,known in themselves, will not be described in detail here.

FIG. 11 also shows the characteristics of the transistor according tothe invention.

The main characteristics of the transistor are an active region formedin layer 102, with rounded edges, a grid 108, 132 self-aligned on thechannel in the active region, an active region protected by aninsulating layer 122 and contacts 150, 152 self-aligned both on the gridand on the insulation layer.

Note that the flanks oxide layer 120 that extends approximatelyperpendicular to the active region avoids any risk of the contact metaloverlapping over the edges of the active area, in other words on theflanks of the portion of thin film forming the active area.

The insulating materials forming the flanks oxide layer 120 and theinsulating layer 122 are not the same. The flanks oxide layer is formedby oxidation whereas the insulation layer 122 is formed by deposition.

Furthermore, the presence of the flanks oxide layer 120 means that anoffset can be formed between the active area and the insulation layer122.

FIG. 11 shows the manufacture of a transistor with a symmetricstructure, and FIG. 12 shows a transistor conform with the invention forwhich the grid structure 132 is offset from the flanks of the insulationlayer 122.

However, the grid is always perfectly aligned with the channel of theactive region. In FIGS. 11 and 12, the channel is shown as reference103.

This figure shows that the contact areas 150, 152 formed on the source140 and drain 142 are self-aligned on the grid and the active area andare laid out directly in contact with the grid structure, in contactwith the lateral spacers. The contact areas 150, 152 form a kind ofsuperelevated and metallized source and drain.

Finally, the process and transistor according to the invention canincrease the integration density, and, as mentioned above, save anexpensive masking step critical for making contacts on source and drain.

What is claimed is:
 1. A process for making a transistor on an SOI typesupport comprising a silicon oxide layer and a thin silicon filmcovering the silicon oxide layer, the process comprising the followingsteps:a) forming a stack comprising a grid insulator layer and a gridmaterial layer in this order on the thin silicon film, b) forming afirst etching mask on the stack according to a pattern corresponding toan active region of the transistor, c) etching the grid material layer,the grid insulation layer and the thin silicon film to form a columnwith first flanks defined according to the pattern of the first etchingmask, d) forming a first insulating layer of electrical insulatingmaterial around the column, and planarizing a surface of this layeruntil the grid material layer of the column is exposed, e) etching thegrid material layer in the column according to a second mask to form agrid structure with second flanks, f) forming a second insulating layerof electrical insulating material on the grid structure so as toelectrically insulate the second flanks of the grid structure, g)forming source and drain regions in the thin silicon film byimplantation of impurities, and h) forming contact areas on the gridstructure in the source and drain regions.
 2. The process according toclaim 1, further comprising:forming a protection layer on the gridmaterial layer during step a), etching the protection layer during stepc), and forming a stop layer by planarizing the surface of the firstinsulating layer in step d), and eliminating the protection layer afterstep d).
 3. The process according to claim 1, wherein the first etchingmask is eliminated before step d).
 4. The process according to claim 1,further comprising:before step d), oxidizing the first flanks of thecolumn formed in step d) to cover the first flanks with flank oxidelayers.
 5. The process according to claim 4, wherein the etching in stepe) is done with a stop on the grid oxide layer and the flank oxidelayers.
 6. The process according to claim 4, wherein the flanks areoxidized with at least one of a high temperature and a high pressure. 7.The process according to claim 1, further comprising:after step d) andafter exposing the grid material layer, forming a shunt layer coveringthe first insulating layer and contacting the grid material layer,wherein the shunt layer is also etched during step e) according to thesecond etching mask, and the second flanks of the grid structureincluding the shunt layer formed during step e) are also electricallyinsulated during step f).
 8. The process according to claim 1, whereinthe step of forming contact areas in step h) comprises a self-aligneddeposition of a metal layer and polishing of this metal layer.
 9. Theprocess according to claim 8, further comprising:eliminating the gridoxide layer exposed on each side of the grid structure during step e)and self-aligned silicidation of the metal layer with the thin siliconfilm exposed by eliminating the grid oxide layer.
 10. The processaccording to claim 8, wherein the metal layer is deposited using achemical vapor phase deposition (CVD) technique.
 11. The processaccording to claim 8, further comprising:forming at least one of anadhesion and a diffusion barrier layer on the first insulating layerbefore deposition of the metal layer.
 12. The process according to claim1, wherein the step of forming the source and drain regions comprises:afirst implantation of doping impurities at a low dose, forming lateralspacers on at least one of 1) the second flanks of the grid structure,2) on the shunt layer, and 3) on the first flanks including the firstinsulating layer, a second implantation of doping impurities at a dosehigher than the dose of the first implantation.
 13. The processaccording to claim 12, wherein the step of forcing lateral spacersincludes the deposition of a layer of silicon nitride and thenanisotropic etching of this layer.
 14. The process according to claim 1,wherein the first insulating layer formed during step d) includes amaterial chosen from PSG and BPSG.
 15. The process according to claim 1,further comprising:forming interconnection lines connected to thetransistor source and drain through contact areas.
 16. The processaccording to claim 2, wherein the protection layer includes siliconnitride.
 17. The process according to claim 2, wherein the grid layer isdoped before the protection layer is eliminated.
 18. The processaccording to claim 1, wherein the grid layer includes material chosenfrom polycrystalline silicon and amorphous silicon.
 19. The processaccording to claim 2, wherein the first etching mask is eliminatedbefore step d).
 20. The process according to claim 2, furthercomprising:before step d), oxidizing the first flanks of the columnformed in step d) to cover the first flanks with flank oxide layers.